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general description the max120/m ax1 22 complete, bicmos, sampling 12-bit analog-to-digital converters (adcs) combine an on-chip track/hold (t/h) and a low-drift voltage reference with fast conversion speeds and low-power consumption. the t/hs 350ns acquisition time combined with the max120s 1.6s conversion time results in throughput rates as high as 500k samples per second (ksps). throughput rates of 333ksps are possible with the 2.6s conversion time of the max122. the max120/max122 accept analog input voltages from -5v to +5v. the only external components needed are decoupling capacitors for the power-supply and refer - ence voltages. the max120 operates with clocks in the 0.1mhz to 8mhz frequency range. the max122 accepts 0.1mhz to 5mhz clock frequencies. the max120/max122 employ a standard microprocessor (p) interface. three-state data outputs are configured to operate with 12-bit data buses. data-access and bus- release timing specifications are compatible with most popular ps without resorting to wait states. in addition, the max120/max122 can interface directly to a first-in, first-out (fifo) buffer, virtually eliminating p interrupt overhead. all logic inputs and outputs are ttl/cmos compatible. for applications requiring a serial interface, refer to the max 121. applications digital-signal processing audio and telecom processing speech recognition and synthesis high-speed data acquisition spectrum analysis data logging systems features 12-bit resolution no missing codes over temperature 20ppm/c -5v internal reference 1.6s conversion time/500ksps throughput (max120) 2.6s conversion time/333ksps throughput (max122) low noise and distortion: ? 70db (min) sinad ? -77db (max) thd (max122) low power dissipation: 210mw separate track/hold control input continuous-conversion mode available 5v input range, overvoltage tolerant to 15v 24-pin narrow dip, wide so, and ssop packages 19-0030; rev 1; 3/12 +denotes a lead(pb)-free/rohs-compliant package. part temp range pin- package inl (lsb) max120cng+ 0c to +70c 24 pdip 1 max120cwg+ 0c to +70c 24 wide so 1 max120cag+ 0c to +70c 24 ssop 1 max120eng+ -40c to +85c 24 pdip 1 max120ewg+ -40c to +85c 24 wide so 1 v dd ain clkin 12 2423 modev ss cs int/busy rd pdip/so/ssop top view 34 2221 d11 d10 d2 56 2019 v ref agnd d0 d1 convst 78 1817 d9 d3 9 16 d8 d4 10 15 d7 d5 11 14 dgnd d6 12 13 max120 max122 + max120/max122 500ksps, 12-bit adcs with track/hold and reference pin coniguration functional diagram ordering information downloaded from: http:///
v dd to dgnd .......................................................... -0.3v to +6v v ss to dgnd ........................................................ +0.3v to -17v ain to agnd ....................................................................... 15v agnd to dgnd ................................................................. 0.3v digital inputs/outputs to dgnd .................... -0.3v to (v + 0.3v) continuous power dissipation (t a = +70c) narrow pdip (derate 13.33mw/c above +70c) .... 1067mw so (derate 11.76mw/c above +70c) ...................... 941mw ssop (derate 8.00mw/c above +70c) ................... 640mw narrow cdip (derate 12.50mw/c above +70c) .... 1000mw operating temperature ranges max12_c ........................................................... 0c to +70c max12_e_ .................................................... -40c to +85c max12_mrg .............................................. -55c to +125c storage temperature range .............................. -65c to+160c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c (v dd = +4.75v to +5.25v, v ss = -10.8v to -15.75v, f clk = 8mhz for max120 and 5mhz for max122, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units accuracy resolution res 12 bits differential nonlinearity (note 1) dnl 12-bit no missing codes over temperature range max122ac/ae 3/4 lsb max120c/e, max122bc/be 1 11-bit no missing codes over temperature range max120m 2 integral nonlinearity (note 1) inl max122ac/ae 3/4 lsb max120c/e, max122bc/be 1 bipolar zero error (note 1) code 00..00 to 00..01 transition, near v ain = 0v 3 lsb temperature drift 0.005 lsb/c full-scale error (notes 1, 2) including reference; adjusted for bipolar zero error; t a = +25c 8 lsb full-scale temperature drift excluding reference 1 ppm/c power-supply rejection ratio (change in fs) (note 3) psrr v dd only, 5v 5% 1/4 3/4 lsb v ss only, -12v 10% 1/4 1 v ss only, -15v 5% 1/4 1 analog inputinput range -5 +5 v input current v ain = +5v (approximately 6k? to ref) 2.5 ma input capacitance (note 4) 10 pf full-power input bandwidth 1.5 mhz reference output voltage no external load, v ain = 5v, t a = +25c -5 02 -4.98 v external load regulation 0ma < i sink < 5ma, v ain = 0v 5 mv temperature drift (note 5) max12_c/e 25 ppm/c max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics downloaded from: http:///
(v dd = +4.75v to +5.25v, v ss = -10.8v to -15.75v, f clk = 8mhz for max120 and 5mhz for max122, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units dynamic performance (max120: f s = 500khz, v ain = 5v p-p , 100khz: max122: f s = 333khz, v ain = 5v p-p , 50khz signal-to-noise plus distortion sinad t a = +25c max120, max122 70 72 db max122ac/ae 70 max122bc/be 69 total harmonic distortion (first five harmonics) thd t a = +25c max120 -82 -77 db max122 -85 -78 max122ac/ae -77 max122bc/be -75 spurious-free dynamic range sfdr t a = +25c max120 77 82 db max122 78 85 max122ac/ae 77 max122bc/be 75 conversion time synchronous t conv 13t clk max120 1.63 s max122 2.60 clock frequency f clk max120 0.1 8 mhz max122 0.1 5 digital inputs (clkin, convst , rd , cs ) input high voltage v ih 2.4 v input low voltage v il 0.8 v input capacitance (note 4) 10 pf input current v in = 0v or v dd 5 a digital outputs ( int / busy , d11Cd0) output low voltage v ol i sink = 1.6ma 0.4 v output high voltage v oh i source = 1ma v dd - 0.5 v leakage current i lkg v in = 0v or v dd , d11Cd0 5 a output capacitance (note 4) 10 pf power requirements positive supply voltage v dd guaranteed by supply rejection test 4.75 5.25 v negative supply voltage v ss guaranteed by supply rejection test -10.80 -15.75 v positive supply current (note 6) i dd v dd = 5.25v, v ss = -15.75v, v ain = 0v 9 15 ma negative supply current (note 6) i ss v dd = 5.25v, v ss = -15.75v, v ain = 0v 14 20 ma power dissipation (note 6) v dd = 5v, v ss = -12v, v ain = 0v 210 315 mw max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
note 1: these tests are performed at v dd = 5v, v ss = -15v. operation over supply is guaranteed by supply rejection tests. note 2: ideal full-scale transition is at +5v - 3/2 lsb = +4.9963v, adjusted for offset error. note 3: supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage = (fs at nomi - nal supply)- (fs at nominal supply tolerance), expressed in lsbs. note 4: for design guidance only, not tested. note 5: temperature drift is defined as the change in output voltage from +25c to t min or t max . it is calculated as t c = v ref / v ref /(t). note 6: v cs = v rd = v convst = 0v, v mode = 5v. note 7: control inputs specified with t r = t f = 5ns ( 10% to 90% of +5v) and timed from a 1.6v voltage level. output delays are measured to +0.8v if going low, or +2.4v if going high. for bus-relinquish time, a change of 0.5v is measured. see figures 1 and 2 for load circuits. note 8: for design guidance only, not tested. (v dd = +5v, v ss = -12v to -15v, 100% tested, t a = t min to t max , unless otherwise noted.) (note 7) parameter symbol conditions t a = +25c max12_c/e units min typ max min typ max cs to rd setup time t cs 0 0 ns cs to rd hold time t ch 0 0 ns convst pulse width t cw 30 30 ns rd pulse width t rw t da t da ns data-access time t da c l = 100pf 40 75 100 ns bus-relinquish time t dh 30 50 65 ns rd or convst to busy t b0 c l = 50pf 30 75 100 ns clkin to busy or int t b1 c l = 50pf 70 110 150 ns clkin to busy low t b2 in mode 5 45 90 120 ns rd to int high t ih c l = 50pf 30 50 75 ns busy or int to data valid t bd c l (data) = 100pf, c l ( int , busy ) = 50pf 20 30 ns acquisition time (note 8) t acq 350 350 ns aperture delay (note 8) t ap 10 ns aperture jitter (note 8) 30 ps pin name function 1 mode mode input. hardwire to set operational mode.v dd : single conversion, int output open: single conversion, busy output dgnd: continuous conversions, busy output 2 v ss negative power supply, -12v or -15v 3 v dd positive power supply, +5v 4 ain sampling analog input, 5v bipolar input range 5 v ref -5v reference output. bypass to agnd with 22f || 0.1f. max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 4 timing characteristics pin description downloaded from: http:///
detailed description adc operation the max120/max122 use successive approximation and input t/h circuitry to convert an analog signal to a series of 12-bit digital-output codes. the control logic interfaces easily to most ps, requiring only a few passive compo - nents tor most applications. the t/h does not require an external capacitor. figure 3 shows the max120/max122 in the simplest operational configuration. analog input track/hold figure 4 shows the equivalent input circuit, illustrating the sampling architecture of the adcs analog comparator. an internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. the analog input appears as a 6k? resistor in parallel with a 10pf capacitor. between conversions, the buffer input is connected to ain through the input resistance. when a conversion starts, the buffer input disconnects from ain, thus sampling the input. at the end of the conversion, the buffer input recon - nects to ain, and the hold capacitor once again charges to the input voltage. the t/h is in tracking mode whenever a conversion is not in progress. hold mode starts approximately 10ns after a conversion is initiated. variation in this delay from one conversion to the next (aperture jitter) is typically 30ps. figures 7 through 11 detail the t/h mode and inter - face timing for the various interface modes. figure 1. load circuits for access time figure 2. load circuits for bus-relinquish time pin name function 6 agnd analog ground 7C11, 13C19 d11Cd0 three-state data outputs d11 (msb) to d0 (lsb) 12 dgnd digital ground 20 convst convert start input. initiates conversions on its falling edge. 21 clkin clock input. drive with ttl-compatible clock from 0.1mhz to 8mhz (max120), 0.1mhz to 5mhz (max122) 22 int / busy interrupt or busy output. indicates converter status. if mode is connected to v dd , conigure for an int output. if mode is open or connected to dgnd, conigure for a busy output. see operational diagrams. 23 cs chip-select input, active-low. when rd is low, enables the three-state outputs. if convst and rd are low, a conversion is initiated on the falling edge of cs . 24 rd read input, active-low. when cs is low, rd enables the three-state outputs. if convst and cs are low, conversion is initiated on the falling egde of rd . max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 5 pin description (continued) downloaded from: http:///
internal reference the max120/max122 -5.00v buried-zener reference biases the internal dac. the reference output is available at the v ref pin and must be bypassed to the agnd pin with a 0.1f ceramic capacitor in parallel with a 22f or greater electrolytic capacitor. the electrolytic capacitors equivalent series resistance (esr) must be 100m? or less to properly compensate the reference output buffer. sanyos organic semiconductor works well. sanyo video components (usa) phone: (619) 661-6835 fax: (619) 661-1055 sanyo electric company, ltd. (japan) phone: 0720-70-1005 fax: 0720-70-1174 sanyo fisher vertriebs gmbh (germany) phone: 06102-27041, ext. 44 fax: 06102-27045 proper bypassing minimizes reference noise and main - tains a low impedance at high frequencies. the internal reference output buffer can sink up to a 5ma external load. an external reference voltage can be used to overdrive the max120/max122s internal reference if it ranges from -5.05v to -5.10v and is capable of sinking a minimum of 5ma. the external v ref bypass capacitors are still required. digital interlace external clock the max120/max122 require a ttl-compatible clock for proper operation. the max120 accepts clocks in the 0.1mhz to 8mhz frequency range when operating in modes 1C4 (see the operating modes section). the maximum clock frequency is limited to 6mhz when oper - ating in mode 5. the max122 requires a 0.1mhz to 5mhz clock for operation in all five modes. the minimum clock frequency for both the max120 and max122 is limited to 0.1mhz, due to the t/hs droop rate. clock and control synchronization the clock and convert start inputs ( convst or rd and cs , see the operating modes section) are not synchro - nized, the conversion time can vary from 13 to 14 clock cycles. the successive approximation register (sar) always changes state on the clkin inputs rising edge. to ensure a fixed conversion time, see figure 5 and the following guidelines. for a conversion time of 13 clock cycles, the convert start input(s) should go low at least 50ns before clkins next rising edge. for a conversion time of 14 clock cycles, the convert start input(s) should go low within 10ns of clkins next rising edge. if the convert start input(s) go low from 10ns to 50ns before clkins next rising edge, the number of clock cycles required is undefined and can be either 13 or 14. for best analog performance, synchro - nize the convert start inputs with the clock input. figure 4. equivalent input circuit figure 3. max120/max122 in the simplest operational mode (continuous conversion) max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 6 downloaded from: http:///
output data format the conversion result is output on a 12-bit data bus with a 75ns data-access time. the output data format is twos- complement. three input control signals ( cs , rd , and convst ), the int / busy converter status output, and the 12 bits of output data can interface directly to a 16-bit data bus. see figure 6 for data-access timing. timing and control the max120/max122 have five operational modes as outlined in figures 7 to 11 and discussed in the operating modes section. full-control mode (mode 1) provides maximum control to the user for convert start and data-read operations. full-control mode is for ps with or without wait-state capability. stand-alone mode (mode 2) and continuous- conversion mode (mode 5) are for systems without ps, or for p-based systems where the adc and the p are linked through first-in, first-out (fifo) buffers or direct memory access (dma) ports. slow-memory mode (mode 3) is intended for ps that can be forced into a wait state during the adcs conversion time. rom mode (mode 4) is for ps that cannot be forced into a wait state. in all five operating modes, the start of a conversion is controlled by one of three digital inputs: convst , rd , or cs . figure 12 shows the logic equivalent for the conver - sion circuitry. in any operating mode, convst must be low for a conversion to occur. once the conversion is in progress, it cannot be restarted. read operations are controlled by rd and cs . both of these digital inputs must be low to read output data. the int / busy output indicates the converters status and determines when the data from the most recent conver - sion is available. the mode input configures the int / busy output as follows: if mode = v dd , int / busy functions as an interrupt output. in this configuration, int / busy goes low when the conversion is complete and returns high after the conversion data has been read. if mode is left open or tied to dgnd , int / busy functions as a busy output. in this case, int / busy goes low at the start of a conversion and remains low until the conversion is complete and the data is avail - able at d0Cd11. figure 5. clock and control synchronization figure 7. full-control mode (mode 1) figure 6. data-access and bus-relinquish timing max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 7 downloaded from: http:///
initialization after power-up on power-up, the first max120/max122 conversion is valid if the following conditions are met: 1) allow 14 clock cycles for the internal t/h to enter the track mode, plus a minimum of 350ns in the track mode for the data-acquisition time. 2) make sure the reference voltage has settled. allow 0.5ms for each 1f of reference bypass capacitance (11ms for a 22f capacitor). operating modesmode 1: (full-control mode) figure 7 shows the timing diagram for full-control mode (mode 1). in this mode, the p controls the conversion- start and data-read operations independently. a falling edge on convst places the t/h into hold mode and starts a conversion in the sar. the conversion is complete in 13 or 14 clock cycles as discussed in the clock and control synchronization section. a change in the int / busy output state signals the end of a conver - sion as follows:if mode = v dd , the end of conversion is signaled by the int/busy output falling edge. if mode = open or dgnd , the int / busy output goes low while the conversion is in progress and returns high when the conversion is complete. when the conversion is complete, the data can be read without initiating a new conversion by pulling rd and cs low and leaving convst high. to start a new conversion without reading data, rd and cs should remain high while convst is driven low. to simultaneous read data and initiate a new conversion, convst , rd , and cs should all be pulled low. note: allow at least 350ns for t/h acquisition time between the end of one conversion and the beginning of the next. mode 2: stand-alone operation (mode= open, rd = cs = dgnd) for systems that do not use or require full-bus interfac - ing, the max120/max122 can be operated in stand-alone mode directly linked to memory through dma ports or a fifo buffer. in stand-alone mode, a conversion is initi - ated by a falling edge on convst . the data outputs are always enabled; data changes at the end of a conversion as indicated by a rising edge on int / busy . see figure 8 for stand-alone mode timing.mode 3: slow-memory mode ( convst = gnd, mode= open) taking rd and cs lo laces the t/h into hold mode and starts a conversion. int / busy remains low while the conversion is in progress and can be used as a wait input to the p. data from the previous conversion appears on the data bus until the conversion end is indicated by int / busy . see figure 9 for slow-memory mode timing. figure 8. stand-alone mode (mode 2) figure 9. slow-memory mode (mode 3) max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 8 downloaded from: http:///
mode 4: rom mode (mode = open, convst = gnd) in rom mode, the max120/max122 behave like a fast- access memory location avoid placing the p into a wait state. pulling rd and cs low places the t/h in hold mode, starts a conversion, and reads data from the previous conversion. data from the first read in a sequence is often disregarded when this interface mode is used. a second read operation accesses the first conversions result and also starts a new conversion. the time between succes - sive read operations must be longer than the sum of the t/h acquisition time and the max120/max122 conver - sion time. see figure 10 for rom-mode timing. mode 5: continuous-conversion mode ( convst = rd = cs = mode = gnd) for systems that do not use or require full-bus interfacing, the max120/max122 can operate in continuous-conver - sion mode, directly linked to memory through dma ports or a fifo buffer. in this mode, conversions are performed continuously at the rate of one conversion for every 14 clock cycles, which includes 2 clock cycles for the t/h acquisition time. to satisfy the 350ns minimum acquisi - tion time requirement within 2 clock cycles, the max120s maximum clock frequency is 6mhz when operating in mode 5. the data outputs are always enabled and new disap - pears on the output bus at the end of a conversion as indicated by the int / busy output rising edge. the mode input should be hard-wired to gnd. pulling cs , rd , or convst high stops conversions. see figure 11 for continuous-conversion mode timing. applications information using fifo buffers using fifo memory to buffer blocks of data from the max120 reduces p interrupt overhead time by enabling the p to process data while the max120, unassisted, writes conversion results to the fifo. to retrieve a block of data, the p reads from the fifo via a read-interrupt cycle. read and write operations for the fifo are com - pletely asynchronous. figure 13 shows the max120 operating in continuous-conversion mode (mode 5),writ - ing data directly into the two idt7200 256 x 9 fifo buf - fers at the rate of 428ksps. the p is interrupted to read the accumulated data by the fifos half-full (hf) flag approximately three times per millisecond. for operation at 500ksps, use an 8mhz clock, and pulse convst at 500khz. the full flag (ff) indicates that the fifo is full. if this flag is ignored, data may be lost. if necessary, con - versions can be inhibited by pulling cs , rd , or convst high. the fifos read cycle times are as fast as 15ns, satisfying most system speed requirements. the reset input resets all data in the fifo to zero. for synchronous operation, the convst pin may be used to initiate conversions, as described in the operating modes section (mode 2: stand-alone operation). figure 10. rom mode (mode 4) figure 11. continuous-conversion mode (mode 5) figure 12. conversion-control logic max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 9 downloaded from: http:///
digital-bus noise if the adcs data bus is active during a conversion, coupling from the data pins to the adc comparator can cause errors. using slow-memory mode (mode 3) avoids this problem by placing the p in a wait state during the conversion. if the data bus is active during the conversion in either mode 1 or 4, use three-state drivers to isolate the bus from the adc. in rom mode (mode 4), considerable digital noise is generated in the adc when rd or cs go high, disabling the output buffers after a conversion is started. this noise can cause errors if it occurs at the same instant the sar latches a comparator decision. to avoid this problem, rd and cs should be active for less than 1 clock cycle. if this is not possible, rd or cs should go high coinciding with clkins falling edge, since the comparator output is always latched at clkins rising edge layout, grounding, and bypassing for best system performance, use pcbs with separate analog and digital ground planes. wire wrap boards are not recommended. the two ground planes should be tied together at the low-impedance power-supply source, as shown in figure 14. the board layout should ensure that digital and analog signal lines are kept separate from each other as much as possible. do not run analog and digital (especially clock) lines parallel to one another. the adcs high-speed comparator is sensitive to high- frequency noise in the v dd and v ss power supplies. bypass these supplies to the analog ground plane with 0.1f and 10f bypass capacitors. minimize capacitor lead lengths for best noise rejection. if the +5v power supply is very noisy, connect a 5? resistor, as shown in figure 14. figure 15 shows the negative power-supply (v ss ) rejection vs. frequency. figure 16 shows the posi - tive power-supply (v dd ) rejection vs. frequency, with and without the optional 5? resistor. figure 13. using max120 with fifo memory max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 10 downloaded from: http:///
gain and offset adjustment figure 17 plots the bipolar input/output transfer func - tion for the max120/max122. code transitions occur halfway between successive integer lsb values. output coding is twos-complement binary with 1 lsb = 2.44mv (10v/4096). in applications where gain (full-scale range) adjustment is required, figure 18s circuit can be used. if both offset and gain (full-scale range) need adjustment, either of the circuits in figures 19 and 20 can be used. offset should be adjusted before gain for either of these circuits. to adjust bipolar offset with figure 19s circuit, apply +1/2 lsb (0.61mv) to the noninverting amplifier input and adjust r4 for output-code flicker between 0000 and 0000 0000 0001. for full scale, apply fs - the output code flick - ers between 0111 1111 1110 and 0111 1111 1111. there may be some interaction between these adjustments. the max120/max122 transfer function used in conjunction with figure 19s circuit is the same as figure 17, except the full-scale range is reduced to 2.5v. to adjust bipolar offset with figure 20s circuit, apply -1/2 lsb (-1.22mv) at v in and adjust r5 for output-code flicker between 0000 0000 0000 and 0000 0000 0001. for gain adjustment, apply -fs + ? lsb (-4.9951v) at v in and adjust r1 so the output code flickers between 0111 1111 1110 and 0111 1111 1111. as with figure 20s circuit, the offset and gain adjustments may interact. figure 21 plots the transfer function for figure 20s circuit. dynamic performance high-speed sampling capability and 500ksps throughput (333ksps for the max122) make the max120/max122 ideal for wideband-signal processing. to support these and other related applications, fast fourier transform (fft) test techniques are used to guarantee the adcs dynamic frequency response, distortion, and noise at the rated throughput. specifically, this involves applying a low- distortion sine wave to the adc input and recording the digital conversion results for a specified time. the data is then analyzed using an fft algorithm, which determines its spectral content. figure 14. power-supply grounding figure 15. v ss power-supply rejection vs. frequency figure 16. v dd power-supply rejection vs. frequency max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 11 downloaded from: http:///
adcs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (inl), and differential nonlinearity (dnl). such parame ters are widely accepted for specifying performance with dc and slowly varying signals, but are less useful in signal processing applications where the adcs impact on the system transfer function is the main concern. the sig nificance of various dc errors does not translate well to the dynamic case, so different tests are required. signal-to-noise ratio and effective number of bits the signal-to-noise plus distortion ratio (sinad) is the ratio of the fundamental input frequencys rms amplitude to the rms amplitude of all other adc output signals. the output band is limited to frequencies above dc and below one-half the adc sample rate. the theoretical minimum adc noise is caused by quanti - zation error and is a direct result of the adcs resolution: snr = (6.02n + 1.76)db, where n is the number of bits of resolution. a perfect 12-bit adc can, therefore, do no better than 74db. an fft plot shows the output level in various spectral bands. figure 22 shows the result of sampling a pure 100khz sinusoid at a 500ksps rate with the max120. by transposing the equation that converts resolution to snr, we can, from the measured sinad, determine the effective resolution (or effective number of bits) the adc provides: n = (sinad - 1.76)/6.02. figure 22 shows the effective number of bits as a function of the input fre - quency for the max120. the max122 performs similarly. figure 17. bipolar transfer function figure 18. trim circuit for gain only figure 19. offset and gain adjustment (noninverting) figure 19. offset and gain adjustment (noninverting) max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 12 downloaded from: http:///
total harmonic distortion if a pure sine wave is sampled by an adc at greater than the nyquist frequency, the nonlinearities in the adcs transfer function create harmonics of the input frequency in the sampled output data. total harmonic distortion (thd) is the ratio of the rms sum of all harmonics (in the frequency band above dc and below one-half the sample rate, but not including the dc component) to the rms amplitude of the fundamental frequency. this is expressed as follows: 222 2 234 n 1 v v v ... v thd 20log v ++ + = where v 1 is the fundamental rms amplitude, and v 2 to v n are the amplitudes of the 2nd through nth harmonics. the thd specification in the electrical characteristics table includes the 2nd through 5th harmonics. lntermodulation distortion if the adc input signal consists of more than one spec - tral component, the adc transfer function nonlinearities produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency if two pure sine waves of frequency fa and fb are applied to the adc input, nonlinearities in the adc transfer func - tion create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. thd includes those distortion products with m or n equal to zero. lntermodulation distortion consists of all distor - tion products for which neither m nor n equal zero. for example, the 2nd-order imd terms include (fa + fb) and (fa - fb) while the 3rd-order imd terms include (2fa + fb), (2fa - fb) , (fa + 2fb), and (fa - 2fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd-order imd products can be expressed by the following formula: amplitude at (fa fb) imd (fa fb) 20log amplitude at fa ?? = ???? figure 21. inverting bipolar transfer function figure 22. max120 fft plot figure 23. effective bits vs. input frequency max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 13 downloaded from: http:///
spurious-free dynamic range spurious-free dynamic range is the ratio of the fundamen - tal rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually the next largest spectral component occurs at some harmonic of the input frequency. however, if the adc is exceptionally linear, it may occur only at a random peak in the adcs noise floor. +denotes a lead(pb)-free/rohs-compliant package. ? max120 ev kit can be used to evaluate the max122; when ordering the ev kit, ask for a free sample of the max122. -denotes a package containing lead(pb). part temp range pin- package inl (lsb) max120eag+ -40c to +85c 24 ssop 1 max122acng+ 0c to +70c 24 pdip 3/4 max122bcng+ 0c to +70c 24 pdip 1 max122acwg+ 0c to +70c 24 wide so 3/4 max122bcwg+ 0c to +70c 24 wide so 1 max122acag+ 0c to +70c 24 ssop 3/4 max122bcag+ 0c to +70c 24 ssop 1 max122aeng+ -40c to +85c 24 pdip 3/4 max122beng+ -40c to +85c 24 pdip 1 max122aewg+ -40c to +85c 24 wide so 3/4 max122bewg+ -40c to +85c 24 wide so 1 max122aeag+ -40c to +85c 24 ssop 3/4 max122beag+ -40c to +85c 24 ssop 1 max122bmrg- -55c to +125c 24 cerdip 1 max120evkit-dip ? 0c to +70c pdip C through hole package type package code outline no. land pattern no. 24 cdip r24-4 21-0045 24 pdip n24+3 21-0043 24 so w24+2 21-0042 90-0182 24 ssop a24+2 21-0056 90-0110 max120/max122 500ksps, 12-bit adcs with track/hold and reference www.maximintegrated.com maxim integrated 14 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information (continued) downloaded from: http:///
revision number revision date description pages changed 0 9/92 initial release 1 3/12 removed pdip, cerdip packages from ordering information . updated style throughout data sheet. 1C16 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max120/max122 500ksps, 12-bit adcs with track/hold and reference ? 2012 maxim integrated products, inc. 15 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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